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Semiconductors & Electronic Devices

Apply concepts from Semiconductors & Electronic Devices to problem-solving. Focus on numerical practice and real-world applications.

2-3 Qs/year45 minPhase 3 · APPLICATION

Concept Core

Energy bands arise because atomic energy levels split when atoms form a solid. The valence band is the highest occupied band, the conduction band is the lowest unoccupied band, and the forbidden energy gap EgE_{g} separates them.
Classification: Conductors (EgE_{g} = 0, bands overlap; examples: Cu, Ag, Al), Semiconductors (EgE_{g} small, 0.1-3 eV; Si: EgE_{g} = 1.1 eV, Ge: EgE_{g} = 0.67 eV), Insulators (EgE_{g} > 3 eV; diamond: EgE_{g} = 5.4 eV).

Intrinsic semiconductors are pure Si or Ge with equal electron and hole concentrations: nen_{e} = nhn_{h} = nin_{i} (intrinsic carrier concentration). Their conductivity increases with temperature (negative temperature coefficient — opposite to metals) because thermal energy excites electrons across the gap.

Extrinsic semiconductors are doped to enhance conductivity.
n-type: pentavalent dopant (P, As, Sb — group 15) donates extra electrons; majority carriers = electrons, minority = holes; nen_{e} >> nhn_{h}.
p-type: trivalent dopant (B, Al, Ga, In — group 13) creates holes (electron deficiency); majority carriers = holes, minority = electrons; nhn_{h} >> nen_{e}.
The mass action law nen_{e} x nhn_{h} = ni2n_{i}^{2} holds for BOTH intrinsic and extrinsic semiconductors — doping increases one carrier type but proportionally decreases the other. Important: n-type and p-type semiconductors are both electrically NEUTRAL (the dopant atoms provide equal numbers of protons).

A p-n junction forms when p-type and n-type materials are joined. Majority carriers diffuse across the junction, creating a depletion region with immobile positive ions on the n-side and negative ions on the p-side. This sets up an internal electric field (from n to p) and a barrier potential (~0.7 V for Si, ~0.3 V for Ge) that opposes further diffusion.

Forward bias (p to +, n to -) reduces the barrier potential, narrows the depletion region, and allows significant current flow once the applied voltage exceeds the knee voltage (~0.7 V Si, ~0.3 V Ge). Reverse bias (p to -, n to +) increases the barrier, widens the depletion region, and allows only a tiny reverse saturation current (due to minority carriers). At high reverse voltage, breakdown occurs (sharp current increase).

The I-V characteristic shows: forward region with exponential rise after knee voltage; reverse region with small constant current until breakdown.

Rectifiers convert AC to pulsating DC. A half-wave rectifier uses one diode (conducts only during positive half cycle; output frequency = input frequency f). A full-wave rectifier uses two diodes with center-tapped transformer or four diodes in a bridge configuration (output frequency = 2f).

Special purpose diodes: The Zener diode is heavily doped and operates in reverse breakdown at a stable voltage VZV_{Z} — used as a voltage regulator. The photodiode operates in reverse bias; incident photons create electron-hole pairs in the depletion region, generating current proportional to light intensity — used in optical communication. The LED (Light Emitting Diode) operates in forward bias; recombination at the junction emits photons with wavelength determined by the semiconductor's band gap (GaAs for IR, GaAsP for red/yellow, GaP for green). The solar cell operates with no external bias; the photovoltaic effect generates an EMF (~0.5-1 V per cell) when light falls on the p-n junction.

Logic gates: OR gate: Y = A + B (output 1 if any input is 1). AND gate: Y = A . B (output 1 only if all inputs are 1). NOT gate: Y = A' (inverts input). NAND gate: Y = (A . B)' (output 0 only when all inputs are 1). NOR gate: Y = (A + B)' (output 1 only when all inputs are 0). NAND and NOR are called universal gates because any Boolean function can be constructed using only NAND gates or only NOR gates. De Morgan's theorems: (A + B)' = A' . B' and (A . B)' = A' + B'.

The key testable concept is logic gate truth tables and identification, combined with p-n junction biasing and special diode applications, which together account for the majority of NEET questions from this chapter.

Solved Numericals

N1. In a pure silicon crystal at 300 K, the intrinsic carrier concentration nin_{i} = 1.5 x 101610^{16} /m3m^{3}.
If the crystal is doped with phosphorus to give nen_{e} = 4.5 x 102210^{22} /m3m^{3}, find the hole concentration. Identify the semiconductor type and majority/minority carriers.

Using mass action law: nen_{e} x nhn_{h} = ni2n_{i}^{2}. nhn_{h} = ni2n_{i}^{2} / nen_{e} = (1.5 x 101610^{16})2 / (4.5 x 102210^{22}) = 2.25 x 103210^{32} / 4.5 x 102210^{22} = 5.0 x 10910^{9} /m3m^{3}.

Semiconductor type: n-type (phosphorus is pentavalent, group 15 dopant; provides extra electrons).

Majority carriers: electrons (nen_{e} = 4.5 x 102210^{22} /m3m^{3}). Minority carriers: holes (nhn_{h} = 5.0 x 10910^{9} /m3m^{3}).

Note: nen_{e} >> nhn_{h} (by a factor of ~101310^{13}), confirming n-type behavior. The hole concentration has decreased dramatically from the intrinsic value (1.5 x 101610^{16}) due to doping — the mass action law ensures that increasing electrons decreases holes proportionally.

N2. Determine the output of the combination: first an OR gate with inputs A and B, then a NOT gate on the output. Write the Boolean expression and truth table. Identify which single gate this combination is equivalent to.

The OR gate output is A + B. The NOT gate inverts this: Y = (A + B)'.

Truth table:

ABA + B (OR output)Y = (A + B)' (final output)
0001
0110
1010
1110

This truth table matches the NOR gate: output is 1 only when ALL inputs are 0.

Boolean expression: Y = (A + B)' — this is exactly the definition of a NOR gate.

By De Morgan's theorem: (A + B)' = A' . B', so the NOR output can also be expressed as "NOT-A AND NOT-B."

Key Testable Concept

By De Morgan's theorem: (A + B)' = A' . B', so the NOR output can also be expressed as "NOT-A AND NOT-B."

Comparison Tables

A) Semiconductor Classification

TypeEnergy Gap (EgE_{g})ExamplesTemperature Effect on ConductivityResistance Coefficient
ConductorEgE_{g} = 0 (bands overlap)Cu, Ag, Al, AuConductivity decreases with temperaturePositive α\alpha (resistance increases)
SemiconductorEgE_{g} small (0.1-3 eV)Si (1.1 eV), Ge (0.67 eV), GaAsConductivity increases with temperatureNegative α\alpha (resistance decreases)
InsulatorEgE_{g} > 3 eVDiamond (5.4 eV), glass, rubberConductivity very low; slight increase at very high TNegative α\alpha

B) n-type vs p-type Comparison

Featuren-typep-type
Dopant valencePentavalent (5 valence electrons)Trivalent (3 valence electrons)
Dopant examplesP (phosphorus), As (arsenic), Sb (antimony)B (boron), Al (aluminum), Ga (gallium), In (indium)
Majority carriersElectronsHoles
Minority carriersHolesElectrons
Energy levelDonor level (just below conduction band)Acceptor level (just above valence band)
Fermi level positionShifts toward conduction bandShifts toward valence band
Carrier relationnen_{e} >> nhn_{h}nhn_{h} >> nen_{e}
Net chargeElectrically neutralElectrically neutral

C) Special Diodes

DiodeBias ConditionWorking PrincipleKey ApplicationMaterial Examples
Zener diodeReverse bias (at breakdown)Constant voltage at breakdown VZV_{Z}Voltage regulatorHeavily doped Si
PhotodiodeReverse biasPhotons create e-h pairs in depletion regionLight detection, optical communicationSi, Ge, InGaAs
LEDForward biase-h recombination emits photonsDisplay, lighting, indicatorsGaAs (IR), GaAsP (red/yellow), GaP (green)
Solar cellNo external biasPhotovoltaic effect generates EMFPower generation, calculatorsSi (crystalline/amorphous)

D) Logic Gates Master Table

GateBoolean ExpressionA=0,B=0A=0,B=1A=1,B=0A=1,B=1Key Property
ORY = A + B0111Output 1 if any input is 1
ANDY = A . B0001Output 1 only if all inputs are 1
NOTY = A'1 (A=0)0 (A=1)Single input; inverts
NANDY = (A . B)'1110Universal gate; output 0 only when all inputs are 1
NORY = (A + B)'1000Universal gate; output 1 only when all inputs are 0
XORY = A xor B0110Output 1 when inputs differ

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